1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to an R-RAM memory using common source and common bit lines to increase the array cell density.
2. Description of the Related Art
The density of memory arrays is limited by the resolution of the interconnect line and transistors features. R-RAM memory arrays typically require word, bit, source, or equivalent lines to read, write, and reset the particular transistors. Thus, even if the transistors can be made smaller by finer resolution processes, the size of the array is limited by the numerous interconnect lines, which have line widths that are likewise limited to the resolution of the process.
Liu, Wu and Ignatiev, in xe2x80x9cElectric-Pulse-Induced reversible resistance change effect in magnetoresistive filmsxe2x80x9d, Applied Physics Letter, Vol. 76, #19, May 8, 2000, revealed their discovery of an electric pulse reversible resistor using a magnetoresistive thin film such as Pr0.7Ca0.3MnO3 on a YBCO (YBa2Cu3O7) bottom electrode. This electrical pulsed reversible property of the disclosed resistor has application in larger scale non-volatile memory array fabrication.
FIG. 1 is a schematic diagram of an R-RAM memory array with a shared source line (prior art). Note, the circuit of FIG. 1 uses a resistor with electrical pulsed reversible properties. The sources of adjacent bit transistors are connected to a common source line, to reduce the cell area. The use of common source lines, as apposed to non-shared source (reference) lines, results in some improvement in density.
FIG. 2 is the partial cross-sectional view of the common source memory array of FIG. 1 (prior art). If the width of the gate lines, the contact holes, the shallow-trench isolation (STI), and the metal lines are all of the minimum feature size, it is possible to run a metal lines for common source interconnect. However, the pitch (the width of a line plus the spacing between two lines) of long metal lines is larger than double the minimum feature size. Therefore, it is not possible to have a metal line contacting each source without increasing the cell size, even if the metal lines are formed on additional (overlying) metal levels.
It would be advantageous if the density of R-RAM memory arrays could be increased by reducing the number of interconnect lines.
It would be advantageous if the interconnect lines of a high density R-RAM array could be made of metal to improve the response times and efficient of the array.
The present invention describes a common bit/common source R-RAM configuration that reduces the cell size and increases the yield of chip fabrication. The configuration eliminates the problem of shorting adjacent bit lines, since the total number of bit lines is approximately halved from non-shared (non-common) bit line configurations.
Accordingly, a common bit/common source line high density 1T1R (one transistor/one resistor) R-RAM array is provided. The R-RAM array comprises a first transistor with a drain connected to a non-shared bit line with a first memory transistor, a second transistor, a third transistor, and a fourth transistor. The gates of the first, second, third, and fourth transistors are connected to a common word line. The R-RAM array comprises at least one common bit line. A second memory resistor is interposed between the drain of the second transistor and the common bit line. Likewise, a third memory resistor is interposed between the drain of the third transistor and the common bit line. In some aspects, a common source line connected to the sources of the third and fourth transistors.
More specifically, the R-RAM array comprises m rows of n sequential transistors, where 71 is an even number, with (nxe2x88x922) interior transistors. The R-RAM array comprises 71 memory resistors, each connected to a corresponding one of the drains of the it transistors. The array comprises m word lines, where each word line is connected to the gates of each of the n transistors in a corresponding row. The R-RAM array comprises ((n/2)xe2x88x921) common bit lines, where each common bit line is operatively connected to a corresponding pair of adjoining interior transistors through corresponding memory resistors, in each row. There are (n/2) common source lines, where each common source line is connected to corresponding pairs of adjoining transistor sources, in each row.
Additional details of the above-described R-RAM array and associated methods for reading, writing, and resetting the R-RAM array are described below.